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800 ma ultralow noise, high psrr, rf linear regulator data sheet ADM7150 features input voltage range: 4.5 v to 16 v maximum output current: 800 ma low n oise 1. 0 v rms total integrated noise from 100 hz to 100 k hz 1.6 v rms total integrated noise from 10 hz to 100 k hz noise spectral density : 1. 7 nvhz typical from 10 khz to 1 mhz power supply rejection ratio ( psrr ) at 400 ma l oad >9 0 db from 1 k hz to 100 k hz , v out = 5 v > 6 0 db at 1 mhz , v out = 5 v dropout voltage: 0.6 v at v out = 5 v , 800 ma load initial v oltage accuracy: 1% voltage accuracy over line, load and temperature : 2% quiescent c urrent ( i gnd ) : 4.3 ma at n o l oad low shutdown current: 0. 1 a stable with a 10 f ceramic output capacitor fixed output voltage options: 1.8 v, 2.8 v, 3.0 v, 3.3 v , 4.5 v, 4.8 v, and 5.0 v ( 16 outputs between 1 .5 v and 5.0 v are available ) exposed pad 8 - lead lfcsp and 8 - lead soic package s applications regulat ed power noise sensitive applications rf mixers, phase - locked loops (plls), voltage - controlled oscillators (vcos), and plls with integrated vcos communications and i nfrastructure cable digital - to - analog converter ( dac ) drivers bac khaul and microwave links typical application circuit vout ref ref_sense gnd vin en byp vreg ADM7150 c reg 10f c byp 1f c ref 1f c in 10f c out 10f off on v in = 6.2v v out = 5.0v 1 1043-001 figure 1. 5 v o utput c irc uit general description the ADM7150 is a low dropout (ldo) linear regulator that opera tes from 4.5 v to 16 v and provides up to 800 ma of output current. using an advanced proprietary architecture, it provides high power supply rejection (>90 db from 1 khz to 1 mhz ), ultra low output noise (<1.7 nvhz), and achieve s excellent line and load t ransient response with a 10 f ceramic output capacitor. the ADM7150 is available in 1.8 v, 2.8 v, 3.0 v, 3.3 v , 4.5 v, 4.8 v, and 5.0 v fixed output s. in addition, 16 fixed output voltages betw een 1 .5 v and 5.0 v are available upon request. the ADM7150 regulator typical output noise is 1. 0 v rms from 1 0 0 hz to 100 k hz for f ixed o utput v oltage o ptions , and the noise spectral density is 1. 7 nv/hz from 10 khz to 1 mhz . the ADM7150 is available in 8 - lead, 3 mm 3 mm lfcsp and 8 - lead soic packages, making it not only a very compact solution but also providing excellent thermal performance for applications requiring up to 800 ma of output current in a small, low profile footprint . see the adm7151 adjustable ldo to generate additional output voltages. 100k 1 10 100 1k 10k 0.1 1 10 100 1k 10k 100k 1m noise spectral density (nv/hz) frequency (hz) c byp = 1f c byp = 10f c byp = 100f c byp = 1mf 1 1043-002 figure 2 . noise spectral density (nsd) vs . frequency for various c byp rev. 0 document feedback info rmation furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specificat ions subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
ADM7150 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor recommended specifications ... 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 15 applications information .............................................................. 16 capacitor selection .................................................................... 16 enable (en) and undervoltage lockout (uvlo) ................. 17 start - up time ............................................................................. 18 ref, byp, an d, vreg pins ........................................................ 18 current - limit and thermal overload protection ................. 19 thermal considerations ............................................................ 19 printed circuit board layout considerations ........................ 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 9 /13 revision 0: initial version rev. 0 | page 2 of 24
data sheet ADM7150 specifications v in = v out + 1. 2 v or v in = 4.5 v , whichever is greater, v en = v in , i out = 10 ma, c in = c out = c reg = 10 f, c ref = c byp = 1 f. t a = 25c for typical specifications . t j = ?40c to +125c for minimum/maximum specifications, unless otherwise noted. table 1 . parameter symbol test conditions /comments min typ max unit input voltage range v in 4.5 16 v operating supply current i gnd i out = 0 a 4.3 7.0 ma i out = 800 ma 8.6 12 ma shutdown current i in - sd v en = 0 v 0.1 3 a output noise out noise 10 hz to 100 khz, i ndependent of output voltage 1.6 v rms 100 hz to 100 khz, i ndependent of output voltage 1. 0 v rms noise spectral density ns d 1 0 khz to 1 mhz, i ndependent of output voltage 1.7 nv/hz power supply rejection ratio psrr 1 k hz to 100 k hz , v in = 6.2 v, v out = 5 v at 800 ma 86 db 1 mhz, v in = 6.2 v, v out = 5 v at 800 ma 54 db 1 k hz to 100 k hz, v in = 6.2 v, v out = 5 v at 400 ma 95 db 1 mhz, v in = 6.2 v, v out = 5 v at 4 00 ma 62 db 1 k hz to 100 k hz, v in = 5 v, v out = 3.3 v at 800 ma 9 4 db 1 mhz, v in = 5 v, v out = 3.3 v at 800 ma 62 db 1 k hz to 100 k hz, v in = 5 v, v out = 3.3 v at 400 ma 95 db 1 mhz, v in = 5 v, v out = 3.3 v at 400 ma 68 db v out v o ltag e accuracy v out = v ref voltage accuracy v out i out = 10 ma , t j = 25c ? 1 +1 % 1 ma < i out < 800 ma , over line, load and temperature ? 2 +2 % v out regulation line regulation v out / v in v in = v out + 1. 2 v or v out + 4.5 v , whichever is greater , to 16 v ? 0 .01 +0.01 %/v load regulation 1 v out / i out i out = 1 ma to 8 00 ma 0. 4 1.0 %/a v out current - limit threshold 2 i limit 1.0 1.2 1.6 a dropout voltage 3 v dropout i out = 400 ma, v out = 5 v 0.3 0. 5 v i out = 800 ma, v out = 5 v 0.6 1. 0 v pull - down resistance v out pull - down resistance v out - pull v en = 0 v, v out = 1 v 600 v reg pull - down resistance v reg - pull v en = 0 v, v reg = 1 v 3 4 k v ref pull - down resistance v ref - pull v en = 0 v, v ref = 1 v 800 v byp pull - down resistance v byp - pull v en = 0 v, v byp = 1 v 500 start - up time 4 v out = 5 v v out start - up t ime t start - up 2.8 ms v reg start - up time t reg - start - up 1.0 ms v ref start - up time t ref - start - up 1.8 ms thermal shutdown thermal shutdown threshold ts sd t j rising 155 c thermal shutdown hysteresis ts sd - hys 15 c undervoltage threshold s input voltage rising uvlo rise 4.49 v input voltage falling uvlo fal l 3.85 v hysteresis uvlo hys 240 mv v reg 5 undervoltage thresholds v reg ris e vreg uvlo rise 3.1 v v reg fall vreg uvlo fal l 2. 55 v hysteresis vreg uvlo hys 2 1 0 mv rev. 0 | page 3 of 24
ADM7150 data sheet parameter symbol test conditions /comments min typ max unit en input 4.5 v v in 16 v en input logic high en high 3. 2 v en input logic low en low 0. 8 v en input logic hysteresis en hys v in = 5 v 225 mv en input leakage current i en - lkg v en = v in or gnd 0.1 1.0 a 1 b ased on an end - point calculation using 1 ma and 800 ma loads. see figure 7 , figure 16 , and figure 22 for typical load regulation performance for loads less than 1 ma . 2 current - limit thre shold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the cur rent limit for a 5 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 5. 0 v, or 4.5 v. 3 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to achieve the nominal output voltage. dropout applies only for output voltages above 4.5 v. 4 start - up time is defined as the time between the rising edg e of v en to v out , v reg , or v ref being at 90% of its nominal value. 5 the output voltage is turned off until the v reg uvlo rise threshold is crossed. the v reg output is turned off until the input voltage uvlo rise threshold is crossed. input and output cap acitor reco mmended specificatio ns table 2 . parameter symbol test conditions /comments min typ max unit capacitance t a = ?40c to +125c minimum input 1 c in 7.0 f minimum regulator 1 c reg 7.0 f minimum output 1 c out 7.0 f minimum bypass c byp 0. 1 f minimum reference c ref 0. 7 f capacitor equivalent series resistance (esr) r esr t a = ?40c to +125c c reg , c out , c in , c ref 0.001 0.2 c byp 0.001 2.0 1 the minimum input, regulator , and output capacitance must be greater than 7.0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7 r and x5r type capacito rs are recommended; however, y5v and z5u capacitors are not recommended for use with any ldo. rev. 0 | page 4 of 24
data sheet ADM7150 absolute maximum rat ings table 3 . parameter rating vin to gnd ? 0.3 v to +1 8 v vreg to gnd ? 0.3 v to vin, or +6 v (whichever is less) vout to gnd ? 0.3 v to vreg, or +6 v (whichever is less) vout to byp 0.3 v en to gnd ? 0.3 v to + 18 v byp to gnd ? 0.3 v to vreg, or +6 v (whichever is less) ref to gnd ? 0.3 v to vreg, or +6 v (whichever is less) ref_sense to gnd ? 0.3 v to +6 v storage temperature range ? 65c to +150c junction temperature 150 c operating ambient temperature range ? 40c to +125c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply i ndividually only, not in combination. the ADM7150 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specifi ed temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low printed circuit board ( pcb ) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), a nd the junction to ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction to ambient thermal re sistance ( ja ) of the package is based on modeling and calculation using a 4 - layer board. the junction to ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in. 3 in. circuit board. see jesd51 - 7 and jesd51 - 9 for detai led information on the board construction. jb is the junction to board thermal characterization parameter with units of c/w. jb of the package is based on modeling and the calculation using a 4 - layer board. the jesd51 - 12, guidelines for reporting and u sing electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance ( jb ) . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temperat ure (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) see jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja , jc , and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc jb unit 8 - lead lfcsp 36.7 23.5 13.3 c/w 8 - lead soic 36.9 27.1 18.6 c/w esd caution rev. 0 | page 5 of 24
ADM7150 data sheet pin configurations a nd function descript i ons 3 by p 4 gnd 1 vreg 2 vout 6 ref 5 ref_sense 8 vin 7 en ADM7150 top view (not to scale) notes 1. exposed pad on the bottom of the package. exposed pad enhances thermal performance and is electrically connected to gnd inside the package. connect the exposed pad to the ground plane on the board to ensure proper operation. 1 1043-003 figure 3. 8 - lead lfcsp pin configuration ADM7150 top view (not to scale) vreg 1 vout 2 by p 3 gnd 4 vin 8 en 7 ref 6 ref_sense 5 1 1043-004 notes 1. exposed pad on the bottom of the package. exposed pad enhances thermal performance and is electrically connected to gnd inside the package. connect the exposed pad to the ground plane on the board to ensure proper operation. figure 4. 8 - lead soic pin configuration table 5 . pin function descriptions pin o. nemonic description 1 vreg regulated i nput supply to ldo amplifier. bypass vreg to gnd with a 10 f or greater capacitor. do not connect a load to ground . 2 vout regulated output voltage. bypass vout to gnd with a 10 f or greater capacitor. 3 byp low noise bypass capacitor. connect a 1 f c apacitor to gnd to reduce noise. do not connect a load to ground. 4 gnd ground connection. 5 ref_sense ref_sense must be connected to the ref pin for proper operation. do not connect to vout or gnd . 6 ref low noise reference voltage output. bypass ref t o gnd with a 1 f capacitor. short ref_sense to ref for fixed output voltages. do not connect a load to ground. 7 en enable. drive en high to turn on the regulator and drive en low to turn off the regulator. for automatic startup, connect en to vin. 8 v in regulator input supply. bypass vin to gnd with a 10 f or greater capacitor. ep ad exposed p ad on the b ottom of the p ackage. the exposed pad enhances thermal performance and is electrically connected to gnd inside the package. connect the exposed pad t o the ground plane on the board to ensure proper operation. rev. 0 | page 6 of 24
data sheet ADM7150 typical performance characteristics v in = v out + 1. 2 v , or v in = 4.5 v , whichever is greater , v en = v in , i out = 10 ma, c in = c out = c reg = 10 f, c ref = c byp = 1 f, t a = 25c, unless otherwise noted . shutdown current (a) temperature (c) ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 ?50 ?25 0 25 50 75 100 125 v in = 6.2v v in = 6.5v v in = 7v v in = 10v v in = 16v 1 1043-005 figure 5 . shutdown current vs. temperature at various input voltages, v out = 5 v v out (v) junction temperature (c) 125 85 25 ?5 ?40 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1043-006 figure 6 . output voltage (v out ) vs. junction temperature (t j ), v out = 5 v v out (v) i load (ma) 1000 100 10 1 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 1 1043-007 figure 7 . output voltage (v out ) vs. load current (i load ), v out = 5 v v out (v) v in (v) 16 12 14 10 8 6 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1043-008 figure 8 . output voltage (v out ) vs. input voltage (v in ), v out = 5 v ground current (ma) junction temperature (c) 125 85 25 ?5 ?40 0 2 4 6 8 10 12 14 16 18 20 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1043-009 figure 9 . ground current vs. junction temperature (t j ), v out = 5 v ground current (ma) i load (ma) 1000 100 10 1 0 1 2 3 4 5 6 7 8 9 10 1 1043-010 figure 10 . ground current vs. load current (i load ), v out = 5 v rev. 0 | page 7 of 24
ADM7150 data sheet ground current (ma) v in (v) 16 15 14 13 12 11 10 9 8 7 6 5 0 1 2 3 4 5 6 7 8 9 10 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1043-0 1 1 figure 11 . ground current vs. input voltage (v in ), v out = 5 v dropout voltage (mv) i load (ma) 1000 100 10 1 0 700 600 500 400 300 200 100 1 1043-012 figure 12 . dropout voltage vs. load cu rrent (i load ), v out = 5 v v out (v) v in (v) 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.0 5.2 5.0 4.8 4.6 4.4 4.2 v dropout = 5ma v dropout = 10ma v dropout = 100ma v dropout = 200ma v dropout = 400ma v dropout = 800ma 1 1043-013 figure 13 . output voltage (v out ) vs. input voltage (v in ) in dropout, v out = 5 v ground current (ma) v in (v) 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 0 12 10 8 6 4 2 i gnd = 5ma i gnd = 10ma i gnd = 100ma i gnd = 200ma i gnd = 400ma i gnd = 800ma 1 1043-014 figure 14 . ground current vs. input voltage (v in ) in dropout, v out = 5 v 11043-015 v out (v) junction temperature (c) 125 85 25 ?5 ?40 3.26 3.27 3.28 3.29 3.30 3.31 3.32 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 15 . output voltage (v out ) vs. junction temperature (t j ), v out = 3.3 v v out (v) i load (ma) 1000 100 10 1 3.26 3.32 3.31 3.30 3.29 3.28 3.27 1 1043-016 figure 16 . output voltage (v out ) vs. load current (i load ), v out = 3.3 v rev. 0 | page 8 of 24
data sheet ADM7150 11043-017 v out (v) v in (v) 16 12 8 14 10 6 4 3.26 3.32 3.31 3.30 3.29 3.28 3.27 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 17 . output voltage (v out ) v s. input voltage (v in ), v out = 3.3 v 11043-018 ground current (ma) junction temperature (c) 125 85 25 ?5 ?40 0 10 9 8 7 6 5 4 3 2 1 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 18 . ground current vs. junction temperature (t j ), v out = 3.3 v ground current (ma) i load (ma) 1000 100 10 1 0 1 2 3 4 5 6 7 8 9 10 1 1043-019 figure 19 . ground current vs. load current (i load ), v out = 3.3 v 1 1043-020 ground current (ma) v in (v) 16 12 8 14 10 6 4 0 10 9 8 7 6 5 4 3 2 1 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 20 . ground current vs. input voltage (v in ), v out = 3.3 v v out (v) junction temperature (c) 125 85 25 ?5 ?40 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1043-021 figure 21 . output voltage (v out ) vs. junction temperature (t j ), v out = 1.8 v 1000 100 10 1 v out (v) i load (ma) 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 1 1043-022 figure 22 . output voltage (v out ) vs. load current (i load ), v out = 1.8 v rev. 0 | page 9 of 24
ADM7150 data sheet 1 1043-023 v out (v) v in (v) 16 10 12 14 8 6 4 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 23 . output voltage (v out ) vs. input voltage (v in ), v out = 1.8 v 1 1043-024 ground current (ma) junction temperature (c) 125 85 25 ?5 ?40 0 10 9 8 7 6 5 4 3 2 1 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 24 . ground current vs. junction temperature (t j ), v out =1.8 v ground current (ma) i load (ma) 1000 100 10 1 0 1 2 3 4 5 6 7 8 9 10 1 1043-025 figure 25 . ground current vs. load current (i load ), v out = 1.8 v 1 1043-026 ground current (ma) v in (v) 16 12 8 14 10 6 4 0 10 9 8 7 6 5 4 3 2 1 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 26 . ground current vs. input voltage (v in ), v out = 1.8 v 1 1043-027 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?120 0 ?20 ?40 ?60 ?80 ?100 load = 800ma load = 400ma load = 200ma load = 100ma load = 10ma figure 27 . power supply rejection ratio (psrr) vs. frequency, v out = 5 v, v in = 6.2 v 1 1043-028 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?120 0 ?20 ?40 ?60 ?80 ?100 400mv 500mv 600mv 700mv 800mv 900mv 1.0v 1.1v 1.2v 1.3v 1.4v 1.5v figure 28 . power supply rejection ratio (psrr) vs. frequency for various headroom voltage , v out = 5 v, 400 ma load rev. 0 | page 10 of 24
data sheet ADM7150 1 1043-029 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?120 0 ?20 ?40 ?60 ?80 ?100 load = 800ma load = 400ma load = 200ma load = 100ma load = 10ma figure 29 . power supply rejection ratio (psrr) vs. frequency, v ou t = 3.3 v, v in = 5 v 1 1043-030 psrr (db) frequency (hz) 10m 1 10 100 1k 10k 100k 1m ?120 0 ?20 ?40 ?60 ?80 ?100 load = 800ma load = 400ma load = 200ma load = 100ma load = 10ma figure 30 . power supply rejection ratio (psrr) vs. frequency, v out = 1.8 v, v in = 5 v 1 1043-031 psrr (db) headroom (v) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 ?120 0 ?20 ?40 ?60 ?80 ?100 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 31 . power supply rejection ratio (psrr) vs. headroom voltage, 100 ma load, v out = 5 v 1 1043-032 psrr (db) headroom (v) 1.5 1.3 1.1 0.9 0.7 0.5 0.3 ?120 0 ?20 ?40 ?60 ?80 ?100 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 32 . power supply rejection ratio (psrr) vs. headroom voltage, 400 ma load, v out = 5 v 1 1043-033 psrr (db) headroom (v) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 ?120 0 ?20 ?40 ?60 ?80 ?100 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 33 . power supply rejection ratio (psrr) vs. headroom voltage, 800 ma load, v out = 5 v 1 1043-034 psrr (db) capacitance (f) 1000 1 10 100 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10hz 100hz 1khz 10khz 100khz 1mhz fig ure 34 . power supply rejection ratio (psrr) vs. c byp , 400 ma load, 400 mv headroom, v out = 5 v rev. 0 | page 11 of 24
ADM7150 data sheet 1 1043-035 psrr (db) capacitance (f) 1000 1 10 100 ?120 ?110 ?100 ?90 ?80 ?70 ?50 ?60 ?40 10hz 100hz 1khz 10khz 100khz 1mhz figure 35 . power supply rejection ratio (psrr) vs. capacitance ( c byp ), 400 ma load, 1.2 v headroom, v out = 5 v 1 1043-036 noise (vrms) load current (ma) 1000 10 100 0 0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.8 1.2 2.0 10hz to 100khz figure 36 . rms output noise vs. load current (i load ) , 10 hz to 100 k hz 1 1043-037 noise (vrms) load current (ma) 1000 10 100 0 0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.8 1.2 2.0 100hz to 100khz figure 37 . rms output noise vs. load current (i load ), 1 00 hz to 100 k hz 1 1043-038 noise spectral density (nv/hz) frequency (hz) 10m 1k 100k 1m 10k 0.1 1 10 figure 38 . outpu t noise spectral density, 1 k hz to 10 mhz, i load = 10 ma 1 1043-039 noise spectral density (nv/hz) frequency (hz) 100k 10k 0.1 1 10 100 1k 1 100k 10k 1k 100 10 figure 39 . output noise spectral density , 0.1 hz to 100 k hz, i load = 10 ma noise spectral density (nv/hz) frequency (hz) 10m 1m 1k 10k 100k 0.1 1 1k 100 10 1 1043-040 load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 40 . output noise spectral density at different load curre nts, 1 k hz to 10 mhz rev. 0 | page 12 of 24
data sheet ADM7150 1 1043-041 noise spectral density (nv/hz) frequency (hz) 100k 0.1 1 10 100 1k 10k 0.1 1 100k 100 1k 10k 10 load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 41 . output noise spectral density at different load currents, 0.1 hz to 10 0 k hz 1 1043-042 noise spectral density (nv/hz) frequency (hz) 1m 0.1 1 10 100 1k 10k 100k 1 100k 100 1k 10k 10 c byp = 1f c byp = 4.7f c byp = 10f c byp = 22f c byp = 47f c byp = 100f c byp = 470f c byp = 1mf figure 42 . output noise spectral density at different c byp , load current = 10 ma ch1 500ma b w ch2 20mv b w m20s a ch1 200ma t 10.40% 1 2 t 1 1043-043 figure 43 . load transient response, i load = 1 ma to 800 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out ch1 500ma b w ch2 10mv b w m4s a ch1 200ma t 11.0% 1 2 t 1 1043-044 figure 44 . load transient response, i load = 10 ma to 800 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out ch1 200ma b w ch2 10mv b w m2s a ch1 460ma t 11.0% 1 2 t 1 1043-045 figure 45 . load transient response, i load = 100 ma to 600 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out ch1 50.0ma b w ch2 2.0mv b w m4s a ch1 50.0ma t 10.0% 1 2 t 1 1043-046 figure 46 . load transient response, i load = 1 ma to100 ma, v out = 5 v , v in = 6.2 v , ch1 = i out , ch2 = v out rev. 0 | page 13 of 24
ADM7150 data sheet ch1 1.0v b w ch2 2.0mv b w m10s a ch1 1.14v t 10.0% 1 2 t 1 1043-047 figure 47 . line transient response, 2 v input step, i load = 800 ma, v out = 1.8 v, v in = 4.5 v , ch1 = v in , ch2 = v out ch1 1.0v b w ch2 2.0mv b w m10s a ch3 1.14v t 10.0% 1 2 t 1 1043-048 figure 48 . line transient response, 2 v in put step, i load = 800 ma, v out = 3.3 v, v in = 4.5 v , ch1 = v in , ch2 = v out ch1 1.0v b w ch2 2.0mv b w m10s a ch3 1.14v t 10.0% 1 2 t 1 1043-049 figure 49 . line transient response, 2 v input step, i load = 800 ma, v out = 5 v, v in = 6.2 v , ch1 = v in , ch2 = v out 1 1043-050 volts time (ms) 10 0 1 2 3 4 5 6 7 8 9 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v en v reg v ref v out figure 50 . v out , v ref , v reg start - up time a fter v en r ising , v out = 3.3 v, v in = 5 v rev. 0 | page 14 of 24
data sheet ADM7150 theory of operation the ADM7150 is a n ultra low noise, high power supply rejection ratio ( psrr ) linear regulator target ing radio frequency ( rf ) applications. the input voltage range is 4.5 v to 16 v , and it can deliver up to 8 00 ma of output current. typical shutdown current consumption is 0. 1 a at room temperature. optimized for use with 1 0 f ceramic capacitors, the ADM7150 provides excellent transient performance. vreg gnd vout vin en ref ref_sense reference shutdown active ripple filter short circuit, thermal protect ota e/a byp 11043-051 figure 51 . simplified internal block diagram internally, the ADM7150 consists of a reference, an error amplifier , and a p - channel mos fet pass transistor . output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the r eference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback v oltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. by heavily filtering the reference voltage , t he ADM7150 is able to achieve 1. 7 nv/hz output typical from 10 khz to 1 mhz . because the error amplifier is always in unity gain, the output noise is independent of the output voltage. t o maintain very high psrr over a wide frequency range, th e ADM7150 architecture uses a n internal active ripple filter . this stage isolate s the low output noise ldo from noise on vin . t he result is that the psrr of the ADM7150 is significantly higher over a wider frequency range than any single stage ldo. the ADM7150 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on, and when en is low , vout turns off. for automatic startup, en can be tied to vin. vreg vin ref_sense ref out byp gnd en 18v 6v 6v 6v 6v 6v 6v 6v 6v 18v 18v 1 1043-052 figure 52 . simplified esd protection block diagram the esd protection device s are shown in the block d iagram as zener diodes (see figure 52). rev. 0 | page 15 of 24
ADM7150 data sheet application s information capacitor selection output capacitor the ADM7150 is designed for operation with ceram ic capacitors but function s with most commonly used capacitors as long as care is taken with regard to the effective series resistance ( esr ) value. the esr of the output capaci tor affects the stabi lity of the ldo control loop . a minimum of 1 0 f capacitanc e with an esr of 0.2 ? or less is recomme nded to ensure the stability of the ADM7150 . output capacitance also affects t ransient response to changes in load current . using a larger value of output capacitance improve s the transient response of the ADM7150 to large changes in load current. figure 53 show s the transient responses for an o utput capacitance value of 1 0 f . ch1 500ma b w ch2 10mv b w m4s a ch1 200ma t 11.0% 1 2 t 1 1043-053 figure 53 . output transient response, v out = 5 v, c out = 1 0 f , ch1 = load current, ch2 = v out input and vreg capacitor connecting a 1 0 f capacitor from v in to gnd reduces the circuit sensitivity to pcb layout, especially wh en long input traces or high source impedance are encountered. to maintain the best possible stability and psrr performance, connect a 10 f capacitor from vreg to gnd. when more than 1 0 f of output capacitance is required, increase the input and vreg ca pacitor s to match it . ref capacitor the ref capacitor i s necessary to stabilize the reference amplifier . connect a t least a 1 f capacitor between r ef and gnd. byp capacitor the byp capacitor is necessary to filter the reference buffer . a 1 f capac itor is typically connected between byp and gnd. capacitors as small as 0.1 f can be used ; however, the output noise voltage of the ldo increase s as a result. in addition, t he byp capacitor value can be increase d to reduce the noise below 1 k hz at the exp ense of increasing the start - up time of the ldo. very large values of c byp significantly reduce the noise below 10 hz. tantalum capacitors are recommended for capacitors larger than approximately 33 f. a 1 f ceramic capacitor in parallel with the larger tantalum capacitor is required to retain good noise performance at higher frequencies. solid tantalum capacitors are less prone to microphonic noise issues. 1 1043-054 noise spectral density (nv/hz) frequency (hz) 1m 0.1 1 10 100 1k 10k 100k 1 100k 100 1k 10k 10 c byp = 1f c byp = 4.7f c byp = 10f c byp = 22f c byp = 47f c byp = 100f c byp = 470f c byp = 1mf figure 54 . noise spectr al density vs . frequency, c byp = 1 f to 1 mf 1 1043-055 noise spectral density (nv/hz) c byp (f) 1000 1 10 100 1 10k 100 1k 10 1hz 10hz 100hz 400hz 3hz 30hz 300hz 1khz figure 55 . noise spectral density vs . capacitance ( c byp ) for different frequencies rev. 0 | page 16 of 24
data sheet ADM7150 capacitor properties any good quality ceramic capacitors can be used with the ADM7150 as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. c apacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions . x5r or x7r dielectrics w ith a voltage rating of 6.3 v to 5 0 v are recommended . however, y5v and z5u dielectri cs are not recommended due to their poor temperature and dc bias characteristics. figure 56 depicts the capacitance vs . dc bias voltage of a 1206, 1 0 f, 1 0 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capa citor size and voltage rati ng. in general, a capacitor in a larger packag e or higher voltage rating exhibit s better stability. the temperature variation of the x5r dielectric is ~ 15% over the ? 40c to + 85c temperature ra nge and is not a function of package or voltage rating. 1 1043-056 capacitance (f) dc bias voltage (v) 10 0 4 8 2 6 0 12 10 8 6 4 2 figure 56 . capacitance vs . dc bias voltage use equation 1 to determine the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficie nt (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 9.72 f at 5 v , as shown in figure 56. substituting these values in equation 1 yields c eff = 9 .72 f (1 ? 0.15) (1 ? 0.1) = 7.44 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the perfo rmance of the ADM7150 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application. enable (en) and u ndervoltage l ocout (uvlo) the ADM7150 use s the en pin to enable and disable the v out pin under normal operating conditions. as shown in figure 57, when a rising voltag e on en crosses the upper threshold, v out turns on. when a falling voltage on en crosses the lower threshold , v out turns off. the hysteresis varies as a function of the input voltag e. for example, the e n hysteresis is approximately 200 mv with an input vol tage of 4.5 v . 1 1043-057 v out (v) v en (v) 1.6 1.5 1.0 1.2 1.4 1.1 1.3 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 vout_en_rise vout_en_fall figure 57 . typical v out response to en pin operation , v out = 3.3 v, v in = 5 v 1 1043-058 en rise threshold (v) v in (v) 16 +125c +25c ?40c 14 12 10 8 6 1.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 figure 58 . typical en ris e threshold vs . input voltage (v in ) for various temperatures rev. 0 | page 17 of 24
ADM7150 data sheet 1 1043-059 en fall threshold (v) v in (v) 16 +125c +25c ?40c 14 12 10 8 6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 figure 59 . typical en fall threshold vs . input voltage (v in ) for various temperatures the ADM7150 also incorporates an internal undervoltage lockout circuit to disable the output voltage w hen the input voltage is less than the minimum input voltage rating of the regulator . the upper and lower thresholds are internally fixed with about 300 mv of hysteresis . 1 1043-060 v out (v) v in (v) 4.5 4.4 4.0 4.2 4.3 4.1 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 vout_vin_rise vout_vin_fall figure 60 . typical uvlo hysteresis , v out = 3.3 v figure 60 shows the typical hysteresis of the uvlo function . this h ysteresis prevents on/off oscillations that can occur due to noise on the input voltage as it passes through the threshold points. s tart - u p t ime the ADM7150 uses an internal soft start to limit the inrush current when the output is enabled. the start - up time for a 5 v o utput is approximately 3 m s from the time the en active threshold is c rossed to when the output reaches 90% of its final value. the rise time of the output voltage (10% to 90%) is approximately 0.0012 c by p s econds where c byp is in microfarads. 1 1043-061 v out (v) time (seconds) 0.020 0.016 0 0.008 0.012 0.004 0.018 0.014 0.006 0.010 0.002 0 6 5 4 3 2 1 enable c byp = 1f c byp = 4.7f c byp = 10f figure 61 . typical start - up behavior with c byp = 1 f to 10 f 1 1043-062 v out (v) time (seconds) 0.20 0.16 0 0.08 0.12 0.04 0.18 0.14 0.06 0.10 0.02 0 6 5 4 3 2 1 enable c byp = 10f c byp = 47f c byp = 330f figure 62 . typical start - up behavior with c byp = 10 f to 330 f r ef , byp, and , vreg pins ref, byp, and vreg are internally generated voltages that require external bypass capacitors for proper operation. do not , unde r any circumstances , connect any loads to these pins because doing so compromise s the noise and psrr performance of the ADM7150 . using larger values of c byp , c ref , and c reg is acceptable but can increase the start - up time as described in the start - up time section. rev. 0 | page 18 of 24
data sheet ADM7150 current - limit and thermal ov erload protection the ADM7150 is protected against d amage due to excessive power dissipation by current and thermal overload protection circuits . the ADM7150 is designed to current - limit when the output load reaches 1.2 a (typical). when the outpu t load exceeds 1 .2 a, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included , which limit s the junction temperature to a maximum of 155c (typical) . under extreme conditions (that is, high ambient temper ature and /or high power dissipation) when the junction temperature starts to rise above 15 5 c, the output is turned off , reduc ing the output current to zero . when the junction temperature drops below 1 40 c, t he output is turned on again , and output current is restored to its operating value . consider the case where a hard short from v out to gnd o ccurs. at first , the ADM7150 current limit s , so that only 1 .2 a is conducted i nto the short. if sel f he ating of the junction is great enough to cause its temperature to rise above 15 5 c , thermal shutdown activ ate s , turning off the output and reducing the output current to zero . as the junction temperature cools and drops below 1 40 c, the output turn s on and conduct s 1 .2 a into the short, again caus ing the junction temperature to rise above 155 c . this thermal oscillation between 1 40 c and 155c cause s a current oscillation between 1 .2 a and 0 ma that continue s as long as the short remains at the output. curr ent - limit and thermal limit protections are intended to protect the device against accidenta l overload conditions. for reliable operation, device power dissipation must be externally limited so that th e junction temperature do es not exceed 15 0 c. thermal c onsiderations in applications with low input to output voltage differential , the ADM7150 does not dissi pate much heat. however, in applications with high a mbient temperature and/or high input vol tage, the heat dis sipated in the package may become large enough that it cause s the junction temperature of the die to exceed the maximum junction temperature of 1 5 0 c. when the junction temperature exceeds 155 c, the converter enters thermal shutdown. it recovers only after the junction temperat ure decrease s below 1 40 c to prevent any permanent damage. therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the ADM7150 must not exceed 15 0 c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient tempe rature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pi n and e xposed pad to the pcb. table 6 shows typical ja values of the 8 - lead soic and 8 - lead lfcsp packages for various pcb copper sizes. table 7 shows the typical jb values of t he 8 - lead soic and 8 - lead lfcsp. table 6 . typical ja values ja (c/w) copper size (mm 2 ) 8 - lead lfcsp 8 - lead soic 25 1 165.1 165 100 125.8 126.4 500 68.1 69.8 1000 56.4 57.8 6400 42.1 43.6 1 device soldered to minimum size pin traces. table 7 . typical jb values package jb (c/w) 8 - lead lfcsp 15.1 8 - lead soic 17.9 the junction temperature of the ADM7150 is calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current , there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 15 0 c. the heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad of the ADM7150 . adding thermal planes under the package also improves thermal performance. however , as listed in table 6 , a point of diminishing returns is eventually reached, beyond which an increase in the copper area does not yield significant reduction in the junction to ambient thermal resistance. rev. 0 | page 19 of 24
ADM7150 data sheet figure 63 to figure 68 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of pcb copper. 1 1043-063 junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 25 35 45 55 65 75 85 95 105 115 125 135 145 155 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 figure 63 . junction temperature vs. total power dissipation for the 8 - lead lfcsp, t a = 25c 11043-064 junction temperature (c) total power dissipation (w) 1.8 2.0 2.2 2.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 50 60 70 80 90 100 110 120 140 160 130 150 6400mm 2 500mm 2 25mm 2 t j max figure 64 . junction temperature vs. total power dissipation for the 8 - lead lfcsp, t a = 50c 1 1043-065 junction temperature (c) total power dissipation (w) 1.5 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 65 75 85 95 105 115 125 135 155 145 6400mm 2 500mm 2 25mm 2 t j max figure 65 . junction temper ature vs. total power dissipation for the 8 - lead lfcsp, t a = 85c 1 1043-066 junction temperature (c) total power dissipation (w) 2.8 2.6 2.4 3.0 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 155 145 125 102 85 65 45 135 115 95 75 55 35 6400mm 2 500mm 2 25mm 2 t j max figure 66 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 25c 1 1043-067 junction temperature (c) total power dissipation (w) 1.8 2.0 2.2 2.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 50 60 70 80 90 100 110 120 130 160 150 140 6400mm 2 500mm 2 25mm 2 t j max figure 67 . junction temperature vs. total p ower dissipation for the 8 - lead soic, t a = 50c 1 1043-068 junction temperature (c) total power dissipation (w) 2.0 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 65 75 85 95 105 115 125 135 155 145 6400mm 2 500mm 2 25mm 2 t j max figure 68 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 85c rev. 0 | page 20 of 24
data sheet ADM7150 thermal characterization parameter ( jb ) when board temperature is known, use the t hermal characterization parameter, jb , to estimate the junction temperature rise (see figure 69 and figure 70 ). maximum j unction temperature (t j ) is calculated from the bo ard temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typical value of jb is 15.1 c/w for t he 8 - lead lfcsp package and 17.9 c/w for the 8 - lead soic package. 11043-069 junction temperature (c) total power dissipation (w) 9.0 8.5 8.0 7.0 6.0 7.5 6.5 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 160 140 120 100 80 60 40 20 t b = 25c t b = 50c t b = 65c t b = 85c t j max figure 69 . junction temperature vs. total power dissipation for the 8 - lead lfcsp 11043-070 junction temperature (c) total power dissipation (w) 5.5 7.5 7.0 6.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 160 140 120 100 80 60 40 20 t b = 25c t b = 50c t b = 65c t b = 85c t j max figure 70 . junction temperature vs. total power dissipation for the 8 - lead soic printed circuit boar d layout considerations place the input capacitor as close as pos sible to the vin and gnd pins. place the output capacitor as close as possible to the vout and gnd pins. place t he bypass capacitors for v reg , v ref , and v byp close to the respective pins and gnd. use of an 0805, 0603, or 0402 size capacitor achieves the sm allest possible footprint solution on boards where area is limited. 1 1043-071 figure 71 . example 8 - lead lfcsp pcb layout 1 1043-072 figure 72 . example 8 - lead soic pcb layout rev. 0 | page 21 of 24
ADM7150 data sheet outline dimensions 2.44 2.34 2.24 t o p view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a se a ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 1 1-28-2012-c 0.20 min figure 73 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 11 ) dimensions shown in millimeters compliant t o jedec s t andards ms-012-a a 06-03-20 1 1-b 1.27 0.40 1.75 1.35 2.41 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarit y 0.10 1.04 ref 8 1 4 5 1.27 bsc sea ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 0.51 0.31 1.65 1.25 3.098 figure 74 . 8 - lead standard small outline package, with exposed pad [soic_n_ep] narro w body (rd - 8- 2) dimensions shown in millimeters ordering guide model 1 temperature range output voltage package description package option branding ADM7150acpz - 1.8-r2 ?40c to +125c 1.8 8 - lead lfcsp_wd cp -8 -11 lp3 ADM7150acpz - 3.3-r2 ?40c to +125c 3.3 8 - lead lfcsp_wd cp -8 -11 lna ADM7150acpz - 4.5-r2 ?40c to +125c 4.5 8 - lead lfcsp_wd cp -8 -11 lnl ADM7150acpz - 4.8-r2 ?40c to +125c 4.8 8 - lead lfcsp_wd cp -8 -11 lnm ADM7150acpz - 5.0-r2 ?40c to +125c 5.0 8 - lead lfcsp_wd cp -8 -11 lnb rev. 0 | page 22 of 24
data sheet ADM7150 model 1 temperature range output voltage package description package option branding ADM7150acpz - 1.8-r7 ?40 c to +125c 1.8 8 - lead lfcsp_wd cp -8 -11 lp3 ADM7150acpz - 3.3-r7 ?40c to +125c 3.3 8 - lead lfcsp_wd cp -8 -11 lna ADM7150acpz - 4.5-r7 ?40c to +125c 4.5 8 - lead lfcsp_wd cp -8 -11 lnl ADM7150acpz - 4.8-r7 ?40c to +125c 4.8 8 - lead lfcsp_wd cp -8 -11 lnm ADM7150 acpz - 5.0 - r7 ?40c to +125c 5.0 8 - lead lfcsp_wd cp - 8 - 11 lnb ADM7150ardz - 1.8 ?40c to +125c 1.8 8 - lead soic_n_ep rd -8 -2 ADM7150ardz - 2.8 ?40c to +125c 2.8 8 - lead soic_n_ep rd -8 -2 ADM7150ardz - 3.0 ?40c to +125c 3.0 8 - lead soic_n_ep rd -8 -2 ADM7150ar dz - 3.3 ?40c to +125c 3.3 8 - lead soic_n_ep rd -8 -2 ADM7150ardz - 5.0 ?40c to +125c 5.0 8 - lead soic_n_ep rd -8 -2 ADM7150ardz - 3.0- r7 ?40c to +125c 3.0 8 - lead soic_n_ep rd -8 -2 ADM7150ardz - 3.3- r7 ?40c to +125c 3.3 8 - lead soic_n_ep rd -8 -2 ADM7150ardz - 5.0- r7 ?40c to +125c 5.0 8 - lead soic_n_ep rd -8 -2 ADM7150cp - evalz 5.0 evaluation board 1 z = rohs compliant part. rev. 0 | page 23 of 24
ADM7150 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11043 - 0 - 9/13(0) rev. 0 | page 24 of 24

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